This application claims the benefit of Korean Patent Application No. 2000-13702, filed Mar. 17, 2000, the disclosure of which is hereby incorporated herein by reference.
The present invention relates generally to manufacturing methods for integrated circuit devices and integrated circuit devices formed thereby and, more particularly, to manufacturing methods for integrated circuit devices having a self-aligned contact and integrated circuit devices formed thereby.
As integrated circuit devices become more highly integrated and include finer geometries, the width and spacing between interconnections have also been reduced. Self-aligned contact technology has been used to increase alignment margins when using photolithography to form contact holes in predetermined regions between interconnections.
Referring now to FIG. 1, a cell array region of a DRAM device may include a plurality of active regions 1, which are formed in a semiconductor substrate and are repeatedly arranged along the X and Y axes. A plurality of parallel word line patterns 3 cross over the active regions 1, with one of the active regions 1xe2x80x2 intersecting two of the word line patterns 3. A plurality of contact patterns 5 may be used to define self-aligned pad contact holes and are respectively arranged on one side of each of the active regions 1. Each of the contact patterns 5 may comprise an etching mask (i.e., a photoresist pattern), which may be used to form the self-aligned contact hole.
FIGS. 2-3, 4A, 4B, and 5-7 are cross-sectional views of the DRAM device of FIG. 1 that illustrate a conventional method that may be used to form a self-aligned contact structure. In each of the figures, the reference symbols xe2x80x9cAxe2x80x9d and xe2x80x9cBxe2x80x9d denote a memory cell region and a peripheral circuit region, respectively. The memory cell regions A of FIGS. 2-3, 4A, and 5-7 are cross-sectional views taken along line Ixe2x80x94I of FIG. 1, and FIG. 4B is a cross-sectional view taken along line IIxe2x80x94II of FIG. 1. To simplify the description, a single NMOS transistor is illustrated in the peripheral circuit region B.
Referring now to FIG. 2, a device isolation layer 13 is formed in a predetermined region of a semiconductor substrate 11 to define active regions therein. A gate oxide layer 15, a conductive layer 17, a capping insulation layer 19, and a hard mask layer 21 are sequentially formed on the entire surface of the resultant structure where the device isolation layer 13 is formed. The capping insulation layer 19 and the hard mask layer 21 are typically made from silicon nitride (SiN) and silicon oxide (SiO2), respectively. The hard mask layer 21, the capping insulation layer 19, and the conductive layer 17 are successively patterned to form a plurality of word line patterns 23a on the active regions and the device isolation layer 13 in the memory cell region A and also to form a gate pattern 23b on the active region in the peripheral circuit region B. Accordingly, each of the word line patterns 23a comprises a word line 17a, a capping insulation layer pattern 19, and a hard mask pattern 21, which are sequentially stacked as shown. Similarly, each gate pattern 23b comprises a gate electrode 17b, a capping insulation layer pattern 19, and a hard mask pattern 21.
Using the word line patterns 23b, the gate pattern 23b, and the device isolation layer 13 as an ion implanting mask, N-type impurities are implanted into the active regions to form low concentration impurity regions 24, 24a, and 24b. In the memory cell region A, the low concentration impurity region 24b formed at a center of the active region corresponds to a common drain region. The low concentration impurity regions 24a correspond to source regions.
Referring now to FIG. 3, a silicon nitride (SiN) layer is formed on an entire surface of the resultant structure and is then anisotropically etched to form spacers 25 on the sidewalls of the word line patterns 23a and the gate pattern 23b. Using the gate pattern 23b, the spacers 25, and the device isolation layer 13 as ion implanting masks, N-type impurities are selectively implanted into the active region of the peripheral circuit region B, thereby forming LDD-typed source/drain regions 26 on opposing sides of the gate pattern 23b. Typically, the impurities are implanted using a high dose of approximately 1xc3x971015 ion atoms/cm2.
An etch-stop layer 27 is then formed on the entire surface of the resultant structure. Typically, the etch-stop layer 27 comprises an insulator, such as silicon nitride (SiN). Next, an interlayer insulation layer 29 is formed on the entire surface of the resultant structure to fill gap regions between the word line patterns 23a as shown in FIG. 3. Typically, the interlayer insulation layer 29 is formed at a temperature of 800xc2x0 C. or lower to prevent degradation of the MOS transistors. Specifically, the low concentration impurity regions 24a and 24b in the memory cell region A and the source/drain regions 26 in the peripheral circuit region B may be re-diffused to reduce the channel length of the transistors when the interlayer insulation layer 29 is made from borophosphosilicate glass (BSPG) that is re-flowed at a high temperature of approximately 850xc2x0 C. to 950xc2x0 C. The interlayer insulation layer 29 is, therefore, typically made of a high-density plasma (HDP) oxide that is capable of filling up the gap regions between the word line patterns 23a without voids at a temperature of 800xc2x0 C. or lower. Furthermore, the interlayer insulation layer 29 is preferably more amenable to etching by a given etchant than the etch-stop layer 27.
When the interlayer insulation layer 29 is made of HDP oxide, however, the power of a high-density plasma apparatus must generally be increased to fill the gap regions between the word line patterns 23a. Unfortunately, if the etch-stop layer 27 has a thickness of approximately 200 xc3x85 or less, then reacting gas used for the high-density plasma process may infiltrate the etch-stop layer 27. As a result, the etch-stop layer 27 may tend to lift from the substrate 11. To suppress this lifting phenomenon, the etch-stop layer 27 may be formed to a thickness of at least 200 xc3x85. But if the thickness of the etch-stop layer 27 is increased, then a lower width of a self-aligned contact hole, which is formed as described hereinafter, may be reduced. Accordingly, it may be difficult to optimize the thickness of the etch-stop layer 27.
Even though the interlayer insulation layer 29 is planarized, a global step difference S1 may be generated between the memory cell region A and the peripheral circuit region B as shown in FIG. 3. Specifically, an upper surface of the interlayer insulation layer 29 in the memory cell region A is lower than that of the peripheral circuit region B. The high-density plasma process, which comprises an alternated and repeated performance of a sputter etching process and a deposition process, may be a cause of the step difference S1. The sputter etching process may exhibit a more efficient etching characteristic in a protrusion region than in a plane region. As a result, the interlayer insulation layer 29 may be etched to a more thin thickness in the memory cell region A, which has a relatively high pattern density, than in the peripheral circuit region B.
Referring now to FIGS. 4A and 4B, a predetermined region of the interlayer insulation layer 29 in the memory cell region A is anisotropically etched using a photo mask on which the contact patterns 5, which are shown in FIG. 1, are drawn. The etch-stop layer 27 is then etched to form self-aligned pad contact holes H1 and H2, which expose the source regions 24a and the common drain region 24b in the memory cell region A. After etching the etch-stop layer 27 to form the pad contact holes H1 and H2, some etch-stop layer residue 27a may remain on a lower sidewall of the self-aligned pad contact holes H1 and H2. Unfortunately, increasing the thickness of the etch-stop layer 27 may also increase the width of the etch-stop layer residue 27a. This may reduce the exposed areas of the source regions 24a and the common drain region 24b, which may reduce an alignment margin between the word line patterns 23a and the active regions.
While performing the photolithographic process for defining the self-aligned pad contact holes H1 and H2, misalignment may also occur along the X-axis shown in FIG. 1. In this case, as shown in FIG. 4B, the source region 24a and the device isolation layer 13 that is adjacent thereto may be exposed by the self-aligned pad contact hole H1. If the interlayer insulation layer 29 is isotropically etched to increase the exposed area of the source regions 24a and the common drain region 24b, then an edge portion R of the exposed device isolation layer 13 may recess to expose a sidewall of a source region 24a. This may lead to an increase injunction leakage current between the semiconductor substrate 11 and a conductive pad filling the self-aligned pad contact hole.
Referring now to FIG. 5, a conductive layer 31 (e.g., a polysilicon layer) is formed on an the entire surface of the resultant structure shown in FIG. 4A in which the self-aligned pad contact holes H1 and H2 are formed. A global step difference S1 between the top surface of the conductive layer 31 in the memory cell region A and the top surface of the conductive layer 31 in the peripheral circuit region B may also be formed as shown in FIG. 5.
Referring now to FIG. 6, the conductive layer 31 and the interlayer insulation layer 29 are etched down to a top surface of the word line patterns 23a of the memory cell region A using, for example, a chemical mechanical polishing (CMP) process. As shown in FIG. 6, a top surface of the word line pattern 23a close to a center of the memory cell region A may be exposed earlier than that of a word line pattern 23a that is adjacent to the peripheral circuit region B. This may be caused by the global step difference S1, which is shown in FIG. 5, and a dishing phenomenon that may accompany the CMP process.
Referring now to FIG. 7, the CMP process used to etch the conductive layer 31 and the interlayer insulation layer 29 to form the electrically isolated conductive pads 31a and 31b in the holes H1 and H2, respectively, may also expose the word lines 17a as shown in FIG. 7. An upper interlayer insulation layer 33 is then formed on the surface of the resultant structure where the conductive pads 31a and 31b are formed. The upper interlayer insulation layer is then patterned to form storage node contact holes 35 that expose the conductive pads 31a, which are in contact with the source regions 24a. 
As discussed hereinabove, it may be difficult to select a suitable thickness for the etch-stop layer 27 because if the etch-stop layer 27 is too thin, then it may lift from the substrate 11 during the HDP process of forming the interlayer insulation layer 29 and if the etch-stop layer 27 is too thick, then a lower width of the self-aligned pad contact holes H1 and H2 may be reduced. Moreover, it may also be difficult to reduce the contact pad resistance and increase alignment margins between the active regions and the word line patterns 23a and between the conductive pads 31a, 31b and the storage node contact holes 35.
Embodiments of the present invention may include integrated circuit devices and methods of manufacturing same in which an insulation layer is selectively etched to increased the self-aligned contact area adjacent a semiconductor region. For example, a pair of interconnection patterns may be formed on a substrate with the substrate having a semiconductor region disposed between the interconnection patterns. An etch-stop layer may then be formed on the pair of interconnection patterns and the substrate, followed by the formation of a sacrificial insulation on the pair of interconnection patterns and on the semiconductor region. The sacrificial insulation layer is then selectively etched to expose portions of the etch-stop layer that extend on the surfaces of the pair of interconnection patterns. Sidewall insulation spacers, which are made of a different material than the sacrificial insulation layer, may then be formed on sidewall portions of the pair of interconnection patterns in an upper gap region between the interconnection patterns and on a portion of the sacrificial insulation layer covering the semiconductor region. The portion of the sacrificial insulation layer that covers the semiconductor region may then be selectively etched, using the sidewall insulation spacers as an etching mask, to define recesses underneath the sidewall insulation spacers. Advantageously, alignment margins of the interconnection patterns may be increased.
In accordance with other embodiments of the present invention, the portion of the etch-stop layer that is exposed when the sacrificial insulation layer is selectively etched to define the recesses underneath the sidewall insulation spacers is etched. A conductive pad may then be formed between the interconnection patterns such that the conductive pad engages the semiconductor region. Because the gap between the pair of interconnection patterns is wider near the substrate due to the recesses defined underneath the sidewall insulation spacers, contact pad resistance may be reduced.
In particular embodiments of the present invention, when the portion of the sacrificial insulation layer covering the semiconductor region is etched to define recesses underneath the sidewall insulation spacers, the sacrificial insulation layer is maintained on the sidewalls of the interconnection patterns. The sacrificial insulation layer residue that remains on the sidewalls of the interconnection patterns may reduce parasitic capacitance between, for example, a word line and a capping insulation layer pattern that comprise each interconnection pattern. In accordance with other embodiments of the present invention, the sacrificial insulation layer is etched until it is removed from the sidewalls of the interconnection patterns.
In accordance with still other embodiments of the present invention, the etch-stop layer and the sidewall insulation spacers are formed of the same material, such as silicon nitride (SiN). Furthermore, the etch-stop layer is preferably formed to a thickness of approximately 200 xc3x85 to 1000 xc3x85. The increased thickness of the etch-stop layer as compared to etch-stop layers typically used in conventional self-aligned contact technology may reduce the tendency for the etch-stop layer to lift from the substrate during formation of the sacrificial insulation layer. Moreover, the increased thickness of the etch-stop layer may protect the source region or drain region from damage when etching the sacrificial insulation layer from the lower gap region.
In accordance with other embodiments of the present invention, the sacrificial insulation layer may comprise a material selected from the group consisting of high density plasma (HDP) oxide, plasma-enhanced tetraethyl ortho silicate (PE-TEOS), and undoped silicate glass (USG). Moreover, the sacrificial insulation layer may be formed at a temperature less than approximately 800xc2x0 C. Advantageously, re-diffusion of the semiconductor region may be reduced.
In accordance with further embodiments of the present invention, integrated circuit devices may be manufactured by forming an isolation layer in a substrate to define a memory cell region and a peripheral circuit region. A pair of word line patterns may be formed on the substrate in the memory cell region and a gate pattern may be formed in the peripheral circuit region. A sacrificial insulation layer may then be formed between the pair of word line patterns such that a gap between the pair of word line patterns is substantially filled. The sacrificial insulation layer is etched such that the sacrificial insulation layer fills a lower gap region that is near the substrate. An interlayer insulation layer is then formed on the memory cell region and the peripheral circuit region such that a distance from an upper surface of the interlayer insulation layer to the substrate surface in the memory cell region is greater than a distance from the upper surface of the interlayer insulation layer to the substrate in the peripheral circuit region. This step difference in the interlayer insulation layer between the memory cell region and the peripheral circuit region is caused by the sacrificial insulation layer that fills the lower gap region between the pair of word line patterns. Advantageously, the step difference may reduce the effects of dishing during subsequent chemical mechanical polishing (CMP) operations that are used to etch back a conductive layer and the interlayer insulation layer to create self-aligned conductive pads between the word line patterns.
In accordance with other embodiments of the present invention, the interlayer insulation layer may be etched from the memory cell region. In addition, the sacrificial insulation layer may be etched to expose the substrate between the word line patterns. A conductive layer may then be formed on the memory cell region and the peripheral circuit region such that a distance form an upper surface of the conductive layer to the substrate surface in the memory cell region is greater than a distance from the upper surface of the conductive layer to the substrate in the peripheral circuit region.
In accordance with still other embodiments of the present invention, the conductive layer in the memory cell region and the conductive layer and the interlayer insulation layer in the peripheral circuit region may be etched, for example, using CMP to form a conductive pad in the gap between the pair of word line patterns.
Thus, the present invention may be used to manufacture integrated circuit devices having increased alignment margins for interconnection patterns formed thereon. In addition, the present invention may be used to manufacture integrated circuit devices having a self-aligned contact that has improved contact pad resistance. Although the present invention has been described above primarily with respect to method aspects of the invention, it will be understood that the present invention may be embodied as methods and/or integrated circuit devices.